Micron MTA36ASF4G72PZ-2G9E2 DDR4 sdram rdim 32gb
MTA36ASF4G72PZ-2G9E2
High-speed DDR4 SDRAM modules use DDR4 SDRAM devices with two or four internal memory bank groups. DDR4 SDRAM modules utilizing 4- and 8-bit-wide DDR4 SDRAM devices have four internal bank groups consisting of four memory banks each, providing a total of 16 banks. 16-bit-wide DDR4 SDRAM devices have two internal bank groups consisting of four memory banks each, providing a total of eight banks. DDR4 SDRAM modules benefit from DDR4 SDRAM's use of an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single READ or WRITE operation for the DDR4 SDRAM effectively consists of a single 8n-bit-wide, four-clock data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
DDR4 modules use two sets of differential signals: DQS_t and DQS_c to capture data and CK_t and CK_c to capture commands, addresses, and control signals. Differentialclocks and data strobes ensure exceptional noise immunity for these signals and pro-vide precise crossing points to capture input signals.
MTA36ASF4G72PZ-2G9E2 - Micron DDR4 SDRAM RDIM 32GB
Product Features
• DDR4 functionality and operations supported as defined in the component data sheet
• 288-pin, registered dual in-line memory module (RDIMM)
• Fast data transfer rates: PC4-3200, PC4-2933, PC4-2666, or PC4-2400
• 32GB (4 Gig x 72)
• VDD = 1.20V (NOM)
• VPP = 2.5V (NOM)
• VDDSPD = 2.5V (NOM)
• Supports ECC error detection and correction
• Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
• Low-power auto self refresh (LPASR)
• On-die VREFDQ generation and calibration
• Dual-rank
• On-board I2C temperature sensor with integrated serial presence-detect (SPD) EEPROM
• 16 internal banks; 4 groups of 4 banks each
• Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS)
• Selectable BC4 or BL8 on-the-fly (OTF)
• Gold edge contacts
• Halogen-free
• Fly-by topology
• Terminated control, command, and address bus